1. Technical Field
This invention generally relates to data processing, and more specifically relates to execution of instructions in a computer system.
2. Background Art
Since the dawn of the computer age, computer systems have evolved into extremely sophisticated devices that may be found in many different settings. Computer systems typically include a combination of hardware (e.g., semiconductors, circuit boards, etc.) and software (e.g., computer programs). The performance of a computer program depends on the ability of the hardware to execute the computer program's instructions.
Some sequences of instructions are executed a relatively large number of times when executing a computer program. For example, a very common sequence of instructions in most computer programs is an add instruction followed by a compare instruction, followed by a branch that determines the program flow depending on the results of the compare instruction. One example of this add-compare-branch sequence is shown by the instructions in FIG. 1. In the prior art, the add operation typically must be completed before starting the compare operation, which in turn must be completed to determine which path the program flow will follow in the computer program when the branch instruction is executed.
In pipelined machines, an instruction pipeline typically attempts to enhance system performance by preloading and pre-executing instructions before they are actually encountered in the code. A conditional branch instruction presents a dilemma for an instruction pipeline. Most known instruction pipelines will pick one of the two possible paths, and will load the pipeline based on the assumed branch direction. If the assumed branch direction is incorrect, the instruction pipeline must invalidate the instructions in the mispredicted path and begin execution from the instruction in the correct branch direction.
When an instruction pipeline mispredicts the direction of a branch, performance penalties result from having to invalidate instructions in the pipeline in the mispredicted branch and execute the instructions in the correct branch path. These performance penalties may become significant. Without a way to improve branch misprediction, the prior art mechanisms and methods for executing instructions will continue to suffer from excessive delays when the direction of a branch is mispredicted by an instruction pipeline.